This article discusses an approach to reducethe structural complexity of binary Galois fields GF(2m) elements multisection multipliers. Elements of fields are represented in a normal basis of type 2. The orderof the fieldreaches998. Multipliers hardware complexity allow their implementation in FPGA. But because of the large structural complexity for some combinations of the fields order and sections number it is almost impossible to make it. The main focus is on reducing of multiplicative matrix structural complexity, which is main part of the multiplier. The article offers a matrix preliminary ordering by special interleaver. Sorting allows to implement a matrix as set of N identical matrixes of AND elements. As a result, it is possible to reduce their number N, hardware and structural complexity by reuse of only one AND matrix. The expected reduction of structural complexity is proportional to N2, one of combinational circuits delay – at times.At the same time, it increases the time complexity of multiplication in N times.Usage of ordered access memory as interleaver should keep multiplier running with different Galois fields.