Scientific and Technical Journal


ISSN Print 2221-3937
ISSN Online 2221-3805
This article analyzes the modes of microprocessors (MP) stellar structure. Well-known mode of MP when arithmetic unit (AP) data in MP and AP AP function together. In this mode, the information is transmitted between the AP during tAP / 2. MP Mode, when the AP and the AP function separately considered in the article on the work in this mode, star-shaped multi-core microprocessor original structure. In this mode, the MP in multi-core parallel structure function microprocessor with direct data flow and a microprocessor with inverted flow data. AP information between these microprocessors transmitted tAP time. In the article as mode MP connecting external devices. In this mode of information between the AP and the AP transmitted during tAP / 2, and in between the outer Story - during tAP. Possible mixed mode IM multi-core structure, where one of the arithmetic units working together, the second part - separately, as part of the AP, the rest - in the mode of connecting external devices. Each of these operating modes set with the correct time charts and signals intended for a certain class of problems, namely processing matrix, solution of differential equations, calculus FFT algorithms and so on.
The positive effect of increased productivity MP structural organizations that dis-considered as well as articles, achieved through the use and further development of their inherent internal parallelism, which allows you to organize various operations in parallel processing of data and their exchange.
1. Broido V.L., and Il'ina O.P. Arkhitek-tura EVM i sistem: Uchebnik dlya vuzov. 2-e izd, [Architecture of Computer and Systems: Textbook for Institutions of Higher Learning], (2009), 2nd Publishing, SPb.: Piter, Russian Federation, 720 p. (In Russian).
2. Mikushin A.V., Sazhnev A.M., and Sedinin V. I. Tsifrovye ustroistva i mikroprot-sessory: ucheb. posobie [Digital Devices and Microprocessors: Manual], (2010), SPb. Pe-terburg, Russian Federation, BKhV, 832 p. (In Russian).
3. Sinegub N.I., and Krisilov V.A., Mik-roprotsessory zvezdoobraznoi struktury povy-shennoi proizvoditel'nosti [Microprocessors of Star-shaped Structure of the Enhanced Pro-ductivity], (2012), Elektrotekhnicheskie i Komp'yuternye Sistemy, No. 7 (83), pp. 85 – 91.
4. Amoretti M., (2014), Modeling and Simulation of Network-on-chip Systems with DEVS and DEUS. The Scientific World Journal, 982569, Vol. 2014 (2014), Article ID 982569, 9 pages, London W1K 6DJ United Kingdom url: doi:
5. Arutyunov P.A., Davydov V.P., Gribkov D.G., and Efimov A.V., (1994), Microprocessors-Element Base of High Productivity Computer for Digital Information Processing. Mikroelektronika, Vol. 23 (4), pp. 19 – 37,
6. Choi Y., Thummadi B.V., Lyytinen K., and Yoo Y., (2012). Analyzing Complex Design Processes: The Effects of Task Automation and Integration on Process Structure in Microprocessor Design. Communications in Computer and Information Science, 286, pp. 38 – 49,
url: журнал Online
7. Dweik W., Annavaram M., and Dubois M., (2014). Reliability-Aware Exceptions: Tolerating Intermittent Faults in Microprocessor Array Structures. Proceed-ings-Design, Automation and Test in Europe, DATE 6800315, 17th Design, Automation and Test in Europe, DATE 2014; Dresden; Ger-many; 24 March 2014 through 28 March 2014; Category numberCFP14162-ART; Code 104993,
url http:
8. Kameyama Michitaka, Amada Tadao, and Higuchi Tatsuo, (1992), Highly Parallel Collision Detection Processor for Intelligent Robots, IEEE Journal of Solid-State Circuits, 27 (4), pp. 500 – 506, University of Michigan Ann Arbor, MI 48109 USA,
9. Paulin P.G., (2004), Date Panel Chips of the Future: Soft, Crunchy or Hard? Proceedings - Design, Automation and Test in Europe Conference and Exhibition, Vol. 2, pp. 844 – 849, US & Canada
10. Proceedings: 34th ACM/IEEE international symposium on microarchitecture, (2001), Proceedings of the Annual International Symposium on Microarchitecture, University of Michigan Ann Arbor, MI 48109 USA url: doi:
11. Ruiz G.A., Michell J.A., and Burón A., (2005), Parallel-pipeline 2-D DCT/IDCT Processor Chip. Proceedings of SPIE – The International Society for Optical Engineering, 5837 (II), 85, 774 – 784,
12. Shazli S.Z., and Tahoori M.B., (2012), Online Detection and Recovery of Transient Errors in Front-end Structures of Micropro-cessors. Proceedings – 2012 17th IEEE Euro-pean Test Symposium, ETS 20126233041, Conference Location :Annecy, url
13. Stepanova L.N., Kabanov S.I., Bekher S.A., and Nikitenko M.S., (2013), Micro-processor Multi-channel Strain-gauge Systems for Dynamic tests of Structures, Automation and Remote Control, Vol. 74 (5), pp. 891 – 897, North & South America,
Last download:
2017-11-16 11:40:30

[ © KarelWintersky ] [ All articles ] [ All authors ]
[ © Odessa National Polytechnic University, 2014. Any use of information from the site is possible only under the condition that the source link! ]